VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages terms of logic density, cost and integration, but also run-time in-field reconfiguration capabilities. However, the current capabilities provided by vendor tools are limited module level. Therefore, incremental configuration memory changes require lengthy compilation time for off-line bitstream generation along storage overheads traditional methodologies. In this paper, internal access port (ICAP) controller that provides versatile fine-grain resource-level programmable (PL) resources SoC is presented. The proposed implemented PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) Flip-Flops (FF). FF achieved through reset after (RAR)-featured partial avoid unintended state corruption other elements. Along versatility, our improves 30 times FFs compared state-of-the-art works while achieving nearly 400-fold increase speed LUTs when vendor-supported software approaches. addition, it achieves competitive resource utilization existing